This invention relates to emulation systems (emulators) used for developing microprocessor-based systems, and specifically to techniques and hardware for mapping memory between emulators and the microprocessor systems under development (target systems).
Emulators aid the development of microprocessor-based systems by providing means for designers to load and run software before any hardware is built. The emulator may substitute for part or all of the target system. As the development approaches completion, functions performed by the emulator are gradually transferred to the target system. During the development, the emulator provides additional microprocessor controls not usually available which are useful for troubleshooting software problems, including: single stepping, break points for certain memory addresses, break points on improper memory accesses, displaying and modifying internal registers, etc.
Emulators may be connected to the target system at any point in the system's development. FIG. 1 is a block diagram of a generic microprocessor-based system, having microprocessor 10, memory 12, and input/output device 14. FIG. 2 is a block diagram of an emulation system, having emulator 18, host computer 20, and user terminal 22. FIG. 3 is a block diagram of an emulator connected to a microprocessor-based system. The emulator is plugged into the microprocessor socket 16 in the target system in place of microprocessor 10 shown in FIG. 1, and is supported by host computer 20. The emulator provides the microprocessor functions and some of the memory for the system, since the user may not have any or all the target system memory functioning. Another advantage of the emulator is that the user may define the proposed Read Only Memory (ROM) memory in the emulator, where it is easily changed, in contrast with the difficulty of changing actual ROM memory in a target system.
Memory mapping is used to define blocks of memory, for example, Random Access Memory (RAM), ROM, guarded or not guarded (accessible during normal run conditions), wait states, etc.; apportion the proposed target system memory by these blocks between the actual available target system memory, if any, and the emulator memory; and control the memory access during actual emulation such that the appropriate memory block, in either target system or emulator memory, is accessed. It is desirable to use blocks of a small size, for example, 256 locations of byte-sized memory (256 bytes), to enable efficient use of memory. If the block size is large, for example, 65,536 bytes, then the user may waste a large amount of memory by dedicating one block to a function which requires only a few hundred bytes. Small block size also enables the user to separate particular error-prone memory blocks from memory-mapped input/output space in the target system which cannot be moved to emulation memory. Since emulation memory and available target system memory are limited in comparison to proposed target system memory, memory space is at a premium during this phase of development of the microprocessor-based system, and consequently small block size is necessary for efficient memory mapping. Additional criteria necessary for efficient memory mapping are the ability to map to any location in the proposed target system memory, and maintaining a high speed of memory access, comparable to the speed of the proposed target system memory.
Target systems access the memory via the memory mapper as shown in FIG. 4. Whether the memory location accessed is actually located in the target system or the emulator is ideally transparent to the target system. One example of a typical prior art memory mapper for a target system using a 24-bit microprocessor, such as the Motorola 68000 microprocessor, encompasses 24 address lines from a microprocessor 24 and an additional 3 function codes for a user memory partition, used for example, to separate the operating system, the user program, and the user data from each other. FIG. 4 shows the connections for the address lines, the data lines, the function code lines, and the status lines. Of the 24 address lines and 3 function code lines from microprocessor 24, the 12 lowest order address lines are connected directly to emulation memory 28, thus defining the mapping block size as 4096 bytes. The upper 12 address lines and the 3 function code lines are connected to memory mapper 26, which determines the user-assigned location for the memory address. The 24 address lines and 3 function code lines also are connected to target system memory 30.
The status lines include a line for target or emulation memory, a line for ROM or RAM, and a line for guarded or not guarded memory access. The target/emulation memory line (control line) connects mapper 26 to switch 32. Mapper 26 determines the actual location of the address, whether in target system memory 30 or emulator memory 28, and a control signal is sent to data switch 32. If mapper 26 determines the actual location of the memory address is in emulator memory 28, the mapper 26 generates the correct higher order address, which is combined with the lower 12 address lines from the microprocessor, and sent to emulator memory 28, which then generates a data output. Target memory 30 also has generated a data output in response to the address on the 24 address lines and the 3 function codes. One of the memories will have the requested data. A control signal from mapper 26 is sent on the control line to switch 32, which connects the correct data lines to microprocessor 24. The entire response of the combined system is ideally equivalent to the completed target system response.
Since the emulation memory is usually much smaller than the addressable memory of a microprocessor, the memory mapper reduces the number of address lines connected to the microprocessor to the number of address lines connected to the emulation memory. For the example above, the size of the emulator memory was chosen to be 2,097,152 bytes. Since the addressable memory for a Motorola 68000 is 16,777,216 bytes, and the 3 function code lines expand this to 134,217,728 bytes, consequently this requires a mapping of memory into 1/64 the available space. The 12 address lines and 3 function code lines entering the mapper 26 become 9 address lines exiting.
FIG. 5 is a block diagram of a prior art memory mapper suitable for mapping 15 memory mapper address lines into 9 emulator memory address lines. This solution translates each address directly into the actual address through the use of 4K byte static RAMs 33. Prior art emulators usually either ignored the function codes or else dealt with the function codes using separate circuitry 34. This leaves only 12 address lines to be mapped. One RAM is required for each emulator memory address bit and for each status bit, consequently 12 RAMs are required for this particular solution. Each RAM uses all the address inputs for the memory mapper. Each address RAM outputs one bit of the emulator memory address. Each status RAM outputs one status condition of the memory location. The address RAM outputs are connected to the emulator memory and the status RAM outputs are connected to the data switch 32 shown in FIG. 4 and other emulator circuitry. This solution is successful if a commercially available RAM exists which has an addressable memory greater than the effective microprocessor addressable memory for the mapper (as defined by both address and function code lines entering the mapper).
When this solution is attempted for a microprocessor having a 32 bit address bus width, it fails because the required RAMs are not currently available. An address bus width of 32 bits plus 5 bits for function codes is an effective width of 37 address lines. Using the same block size as the prior art example above but with 37 address lines, results as follows: 37 total address lines less 12 unmapped lines (block size) results in 25 address lines to the mapper 26. Twenty-five address lines to the mapper implies that the RAMs used would have 25 address lines and therefore be a 33,554,432 byte (33.6 Megabyte) static RAM, which is probably many years away. This solution could be used with currently available 65,536-byte static RAMs for mapping 16 of the address lines, but the remaining 21 address lines would connect directly to the emulation memory, causing the block size to increase to 2,097,152 bytes, which would allow only one definition for the example of 2,097,152 bytes of emulator memory.